PCA9306 Level Translator Breakout - Revision history

Admin: /* How to buy */

2014-10-28T06:01:29Z

How to buy

← Older revision		Revision as of 06:01, 28 October 2014
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	==How to buy==		==How to buy==
	Click here to buy [PCA9306 Level Translator Breakout]		Click here to buy [http://www.geeetech.com/pca9306-level-translator-breakout-p-654.html PCA9306 Level Translator Breakout]

Admin: /* Usage */

2013-01-23T07:26:55Z

Usage

← Older revision		Revision as of 07:26, 23 January 2013
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	==Usage==		==Usage==
	[[File:PCA93061.jpg\|~~500px~~]]		[[File:PCA93061.jpg\|600px]]

	==Document==		==Document==

Admin at 07:15, 23 January 2013

2013-01-23T07:15:43Z

← Older revision		Revision as of 07:15, 23 January 2013
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	==Usage==		==Usage==
			[[File:PCA93061.jpg\|500px]]

	==Document==		==Document==
			[http://www.nxp.com/documents/data_sheet/PCA9306.pdf PCA9306 Datasheet]

	==How to buy==		==How to buy==
	Click here to buy [PCA9306 Level Translator Breakout]		Click here to buy [PCA9306 Level Translator Breakout]

Admin at 06:53, 23 January 2013

2013-01-23T06:53:19Z

← Older revision		Revision as of 06:53, 23 January 2013
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	== ~~introduction~~ ==		== Overview ==
	[[File:PCA9306.jpg\|300px]]		[[File:PCA9306.jpg\|300px]]

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	==Features ==		==Features==

	*2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications		*2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications
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	*Provides bidirectional voltage translation with no direction pin		*Provides bidirectional voltage translation with no direction pin
	*Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion		*Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion

			==Usage==

			==Document==

			==How to buy==
			Click here to buy [PCA9306 Level Translator Breakout]

Admin at 06:21, 23 January 2013

2013-01-23T06:21:51Z

← Older revision		Revision as of 06:21, 23 January 2013
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	*Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters		*Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters
	*Allows voltage level translation between:		*Allows voltage level translation between:
	1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias <br>		**1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias <br>
	1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias<br>		**1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias<br>
	1.8 V Vref(1)and 3.3 V or 5 V Vbias<br>		**1.8 V Vref(1)and 3.3 V or 5 V Vbias<br>
	2.5 V Vref(1) and 5 V Vbias<br>		**2.5 V Vref(1) and 5 V Vbias<br>
	3.3 V Vref(1) and 5 V Vbias<br>		**3.3 V Vref(1) and 5 V Vbias<br>
	*Provides bidirectional voltage translation with no direction pin		*Provides bidirectional voltage translation with no direction pin
	*Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion		*Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion

Admin at 06:21, 23 January 2013

2013-01-23T06:21:02Z

← Older revision		Revision as of 06:21, 23 January 2013
Line 13:		Line 13:
	*Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters		*Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters
	*Allows voltage level translation between:		*Allows voltage level translation between:
	1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias <br>		1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias <br>
	1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias		1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias<br>
	1.8 V Vref(1)and 3.3 V or 5 V Vbias		1.8 V Vref(1)and 3.3 V or 5 V Vbias<br>
	2.5 V Vref(1) and 5 V Vbias		2.5 V Vref(1) and 5 V Vbias<br>
	3.3 V Vref(1) and 5 V Vbias		3.3 V Vref(1) and 5 V Vbias<br>
	*Provides bidirectional voltage translation with no direction pin		*Provides bidirectional voltage translation with no direction pin
	*Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion		*Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion

Admin at 06:20, 23 January 2013

2013-01-23T06:20:29Z

← Older revision		Revision as of 06:20, 23 January 2013
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	[[File:PCA9306.jpg\|300px]]		[[File:PCA9306.jpg\|300px]]

	This is a breakout board for the PCA9306 dual bidirectional voltage-level translator.		This is a breakout board for the PCA9306 dual bidirectional voltage-level translator. Because different parts sometimes use different voltage levels to communicate, voltage level translators can be the key to making different parts play nice.

	~~Because different parts sometimes use different~~ voltage ~~levels~~ to ~~communicate~~,		The PCA9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator that's operational on the low side from 1.0 V to 3.6 V and on the high side from 1.8 V to 5.5 V. Simply apply your low- and high-side reference voltages to the VREF1 and VREF2 respectively, connect your I/O and drive the Enable pin high to open bidirectional voltage translation without the use of a direction pin!

	~~voltage level translators can be the key to making different parts play nice.~~

	==Features ==		==Features ==

	* 2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications		*2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications
	* Standard-mode, Fast-mode, and Fast-mode Plus I2C-bus and SMBus compatible		*Standard-mode, Fast-mode, and Fast-mode Plus I2C-bus and SMBus compatible
	* Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters		*Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters
	* Allows voltage level translation between:		*Allows voltage level translation between:
	1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias~~(ref)(2)~~		1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias <br>
			1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias
	1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias~~(ref)(2)~~		1.8 V Vref(1)and 3.3 V or 5 V Vbias
			2.5 V Vref(1) and 5 V Vbias
	1.8 V Vref(1)and 3.3 V or 5 V Vbias~~(ref)(2)~~		3.3 V Vref(1) and 5 V Vbias
			*Provides bidirectional voltage translation with no direction pin
	2.5 V Vref(1) and 5 V Vbias~~(ref)(2)~~		*Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion

	3.3 V Vref(1) and 5 V Vbias~~(ref)(2)~~
	* Provides bidirectional voltage translation with no direction pin
	* Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion

Admin: /* introduction */

2013-01-18T02:09:09Z

introduction

← Older revision		Revision as of 02:09, 18 January 2013
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	== introduction ==		== introduction ==
	[[File:PCA9306.jpg]]		[[File:PCA9306.jpg\|300px]]

	This is a breakout board for the PCA9306 dual bidirectional voltage-level translator.		This is a breakout board for the PCA9306 dual bidirectional voltage-level translator.
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	voltage level translators can be the key to making different parts play nice.		voltage level translators can be the key to making different parts play nice.


	==Features ==		==Features ==

Admin at 01:55, 18 January 2013

2013-01-18T01:55:42Z

← Older revision		Revision as of 01:55, 18 January 2013
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	* Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters		* Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters
	* Allows voltage level translation between:		* Allows voltage level translation between:
	1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2);		1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
	1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2);
	1.8 V Vref(1)and 3.3 V or 5 V Vbias(ref)(2);		1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)
	2.5 V Vref(1) and 5 V Vbias(ref)(2);
	3.3 V Vref(1) and 5 V Vbias(ref)(2);		1.8 V Vref(1)and 3.3 V or 5 V Vbias(ref)(2)

			2.5 V Vref(1) and 5 V Vbias(ref)(2)

			3.3 V Vref(1) and 5 V Vbias(ref)(2)
	* Provides bidirectional voltage translation with no direction pin		* Provides bidirectional voltage translation with no direction pin
	* Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion		* Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion

Admin at 01:54, 18 January 2013

2013-01-18T01:54:42Z

← Older revision		Revision as of 01:54, 18 January 2013
Line 15:		Line 15:
	* Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters		* Less than 1.5 ns maximum propagation delay to accommodate Standard-mode and Fast-mode I2C-bus devices and multiple masters
	* Allows voltage level translation between:		* Allows voltage level translation between:
	**1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)		1.0 V Vref(1) and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2);
	~~**1~~.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2)		1.2 V Vref(1)and 1.8 V, 2.5 V, 3.3 V or 5 V Vbias(ref)(2);
	**1.8 V Vref(1)and 3.3 V or 5 V Vbias(ref)(2)		1.8 V Vref(1)and 3.3 V or 5 V Vbias(ref)(2);
	**2.5 V Vref(1) and 5 V Vbias(ref)(2)		2.5 V Vref(1) and 5 V Vbias(ref)(2);
	**3.3 V Vref(1) and 5 V Vbias(ref)(2)		3.3 V Vref(1) and 5 V Vbias(ref)(2);
	* Provides bidirectional voltage translation with no direction pin		* Provides bidirectional voltage translation with no direction pin
	* Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion		* Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion